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450 MHz to 6000 MHz TruPwr Detector ADL5504
FEATURES
True rms response detector Excellent temperature stability 0.25 dB rms detection accuracy vs. temperature Over 35 dB input power dynamic range, inclusive of crest factor RF bandwidths from 450 MHz to 6000 MHz 500 input impedance Single-supply operation: 2.5 V to 3.3 V Low power: 1.8 mA at 3.0 V supply RoHS compliant part
FUNCTIONAL BLOCK DIAGRAM
VPOS
ENBL
ADL5504
1k
INTERNAL FILTERING FLTR
RFIN
RMS CORE BUFFER
100 VRMS
COMM
Figure 1.
APPLICATIONS
Power measurement of W-CDMA, CDMA2000, QPSK-/QAMbased OFDM (LTE and WiMAX), and other complex modulation waveforms RF transmitter or receiver power measurement
OUTPUT (V) 10
1
0.1
-20
-15
-10
-5
0
5
10
15
INPUT (dBm)
Figure 2. Output vs. Input Level, 3 V Supply, Frequency 1900 MHz
GENERAL DESCRIPTION
The ADL5504 is a TruPwrTM mean-responding (true rms) power detector for use in high frequency receiver and transmitter signal chains from 450 MHz to 6000 MHz. Requiring only a single supply between 2.5 V and 3.3 V, the detector draws less than 1.8 mA. The input is internally ac-coupled and has a nominal input impedance of 500 . The rms output is a linear-responding dc voltage with a conversion gain of 1.87 V/V rms at 900 MHz. The ADL5504 is a highly accurate, easy to use means of determining the rms of complex waveforms. It can be used for power measurements of both simple and complex waveforms but is particularly useful for measuring high crest factor (high peak-to-rms ratio) signals, such as W-CDMA, CDMA2000, WiMAX, WLAN, and LTE waveforms. The on-chip modulation filter provides adequate averaging for most waveforms. For more complex waveforms, an external capacitor at the FLTR pin can be used for supplementary signal demodulation. An on-chip, 100 series resistance at the output, combined with an external shunt capacitor, creates a low-pass filter response that reduces the residual ripple in the dc output voltage. The ADL5504 offers excellent temperature stability across a 30 dB range and near 0 dB measurement error across temperature over the top portion of the dynamic range. In addition to its temperature stability, the ADL5504 offers low process variations that further reduce calibration complexity. The power detector operates from -40C to +85C and is available in a 6-ball, 0.8 mm x 1.2 mm, wafer level chip scale package. It is fabricated on a high fT silicon BiCMOS process.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
08437-002
0.01 -25
08437-001
ADL5504 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Circuit Description ......................................................................... 13 RMS Circuit Description and Filtering ................................... 13 Filtering ........................................................................................ 13 Output Buffer .............................................................................. 13 Applications Information .............................................................. 14 Basic Connections ...................................................................... 14 RF Input Interfacing................................................................... 14 Linearity....................................................................................... 15 Output Drive Capability and Buffering................................... 16 Selecting the Square-Domain Filter and Output Low-Pass Filter ............................................................................................. 16 Power Consumption, Enable, and Power-On/Power-Off Response Time ............................................................................ 17 Device Calibration and Error Calculation .............................. 17 Calibration for Improved Accuracy ......................................... 18 Drift over a Reduced Temperature Range .............................. 19 Device Handling ......................................................................... 19 Evaluation Board ........................................................................ 20 Outline Dimensions ....................................................................... 22 Ordering Guide .......................................................................... 22
REVISION HISTORY
10/09--Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADL5504 SPECIFICATIONS
TA = 25C, VS = 3.0 V, CFLTR = 10 nF, COUT = open, light condition 600 lux, 75 input termination resistor, unless otherwise noted. Table 1.
Parameter FREQUENCY RANGE RF INPUT (f = 450 MHz) Input Impedance RMS Conversion Dynamic Range 1 0.25 dB Error 2 0.25 dB Error 3 1 dB Error3 2 dB Error3 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept 4 Output Voltage, High Input Power Output Voltage, Low Input Power Temperature Sensitivity Test Conditions Input RFIN Input RFIN to output VRMS No termination Continuous wave (CW) input, -40C < TA < +85C Delta from 25C Min 450 Typ Max 6000 Unit MHz ||pF
520||1.00
0.25 dB error3 1 dB error3 VRMS = (gain x VIN) + intercept PIN = 5 dBm, 400 mV rms PIN = -15 dBm, 40 mV rms PIN = 0 dBm 25C < TA < 85C -40C < TA < +25C Input RFIN to output VRMS No termination CW input, -40C < TA < +85C Delta from 25C
25 16 35 39 15 -21 1.90 0.003 0.760 0.077 0.0027 0.0024 370||0.80
dB dB dB dB dBm dBm V/V rms V
dB/C dB/C ||pF
RF INPUT (f = 900 MHz) Input Impedance RMS Conversion Dynamic Range1 0.25 dB Error2 0.25 dB Error3 1 dB Error3 2 dB Error3 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept4 Output Voltage, High Input Power Output Voltage, Low Input Power Temperature Sensitivity
0.25 dB error3 1 dB error3 VRMS = (gain x VIN) + intercept PIN = 5 dBm, 400 mV rms PIN = -15 dBm, 40 mV rms PIN = 0 dBm 25C < TA < 85C -40C < TA < +25C
1.6 -0.1
27 17 35 39 15 -22 1.87 +0.004 0.746 0.077 0.0024 0.0018
2.2 +0.1
dB dB dB dB dBm dBm V/V rms V V V dB/C dB/C
Rev. 0 | Page 3 of 24
ADL5504
Parameter RF INPUT (f = 1900 MHz) Input Impedance RMS Conversion Dynamic Range1 0.25 dB Error2 0.25 dB Error3 1 dB Error3 2 dB Error3 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept4 Output Voltage, High Input Power Output Voltage, Low Input Power Temperature Sensitivity Test Conditions Input RFIN to output VRMS No termination CW input, -40C < TA < +85C Delta from 25C Min Typ 260||0.68 Max Unit ||pF
0.25 dB error3 1 dB error3 VRMS = (gain x VIN) + intercept PIN = 5 dBm, 400 mV rms PIN = -15 dBm, 40 mV rms PIN = 0 dBm 25C < TA < 85C -40C < TA < +25C Input RFIN to output VRMS No termination CW input, -40C < TA < +85C Delta from 25C
20 15 35 40 15 -22 1.82 0.001 0.719 0.072 0.0016 0.0070 240||0.61
dB dB dB dB dBm dBm V/V rms V V V dB/C dB/C ||pF
RF INPUT (f = 2600 MHz) Input Impedance RMS Conversion Dynamic Range1 0.25 dB Error2 0.25 dB Error3 1 dB Error3 2 dB Error3 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept4 Output Voltage, High Input Power Output Voltage, Low Input Power Temperature Sensitivity
0.25 dB error3 1 dB error3 VRMS = (gain x VIN) + intercept PIN = 5 dBm, 400 mV rms PIN = -15 dBm, 40 mV rms PIN = 0 dBm 25C < TA < 85C -40C < TA < +25C Input RFIN to output VRMS No termination CW input, -40C < TA < +85C Delta from 25C
13 10 35 40 15 -22 1.79 -0.003 0.702 0.069 0.0031 0.0046 200||0.50
dB dB dB dB dBm dBm V/V rms V V V dB/C dB/C ||pF
RF INPUT (f = 3500 MHz) Input Impedance RMS Conversion Dynamic Range1 0.25 dB Error2 0.25 dB Error3 1 dB Error3 2 dB Error3 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept4 Output Voltage, High Input Power Output Voltage, Low Input Power Temperature Sensitivity
0.25 dB error3 1 dB error3 VRMS = (gain x VIN) + intercept PIN = 5 dBm, 400 mV rms PIN = -15 dBm, 40 mV rms PIN = 0 dBm 25C < TA < 85C -40C < TA < +25C
6 5 34 40 13 -21 1.65 -0.006 0.639 0.060 0.0037 0.0074
dB dB dB dB dBm dBm V/V rms V V V dB/C dB/C
Rev. 0 | Page 4 of 24
ADL5504
Parameter RF INPUT (f = 6000 MHz) Input Impedance RMS Conversion Dynamic Range1 1 dB Error3 2 dB Error3 Maximum Input Level Minimum Input Level Conversion Gain Output Intercept4 Output Voltage, High Input Power Output Voltage, Low Input Power Temperature Sensitivity Test Conditions Input RFIN to output VRMS No termination CW input, -40C < TA < +85C 25 34 12 -16 0.82 -0.005 0.314 0.027 0.0108 0.0120 10 2.5 3 3 100 dB dB dBm dBm V/V rms V V V dB/C dB/C mV V mA s Min Typ 90||0.31 Max Unit ||pF
0.25 dB error3 1 dB error3 VRMS = (gain x VIN) + intercept PIN = 5 dBm, 400 mV rms PIN = -15 dBm, 40 mV rms PIN = 0 dBm 25C < TA < 85C -40C < TA < +25C Pin VRMS No signal at RFIN VS = 3.0 V, RLOAD 10 k 10 dB step, 10% to 90% of settling level, no filter capacitor Pin ENBL 2.5 V VS 3.3 V, -40C < TA < +85C 2.5 V at ENBL, -40C < TA < +85C 2.5 V VS 3.3 V, -40C < TA < +85C CFLTR = open, 0 dBm at RFIN CFLTR = 10 nF, 0 dBm at RFIN -40C < TA < +85C No signal at RFIN, ENBL high input condition ENBL input low condition
VRMS OUTPUT Output Offset Maximum Output Voltage Available Output Current Pulse Response Time ENABLE INTERFACE Logic Level to Enable Power, High Condition Input Current when High Logic Level to Disable Power, Low Condition Power-Up Response Time 5 POWER SUPPLIES Operating Range Quiescent Current 6 Disable Current 7
1 2 3
1.8 0.05 -0.5 1 8 2.5 1.8 0.1
VPOS 0.1 +0.5
V A V s s V mA A
3.3 1
The available output swing and, therefore, the dynamic range are altered by the supply voltage; see Figure 8. Error referred to delta from 25C response; see Figure 13 to Figure 15 and Figure 19 to Figure 21. Error referred to best-fit line at 25C; see Figure 10 to Figure 12 and Figure 16 to Figure 18. 4 Calculated using linear regression. 5 The response time is measured from 10% to 90% of settling level; see Figure 31 to Figure 33. 6 Supply current is input level-dependent; see Figure 27. 7 Guaranteed but not tested; limits are specified at six sigma levels.
Rev. 0 | Page 5 of 24
ADL5504 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage, VS VRMS, ENBL RFIN Equivalent Power, Referred to 50 Internal Power Dissipation JA (WLCSP) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 3.5 V 0 V to VS 1.25 V rms 15 dBm 150 mW 260C/W 125C -40C to +85C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. 0 | Page 6 of 24
ADL5504 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
FLTR 1 6 ENBL
VPOS
2
5
VRMS
RFIN
3
4
COMM
ADL5504
TOP VIEW (BALL SIDE DOWN) Not to Scale
08437-003
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5 Mnemonic FLTR VPOS RFIN COMM VRMS Description Modulation Filter. Connect an external capacitor to this pin to lower the corner frequency of the modulation filter. Supply Voltage. The operational range is 2.5 V to 3.3 V. Signal Input. This pin is internally ac-coupled after internal termination resistance. The nominal input impedance is 500 . Device Ground. RMS Output. This pin is a rail-to-rail voltage output with limited current drive capability. The output has an internal 100 series resistance. High resistive loads and low capacitance loads are recommended to preserve output swing and allow fast response. Enable. Connect this pin to VS for normal operation. Connect this pin to ground for disable mode.
6
ENBL
Rev. 0 | Page 7 of 24
ADL5504 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C, VS = 3.0 V, CFLTR = 10 nF, COUT = open, light condition 600 lux, 75 input termination resistor; colors: black = +25C, blue = -40C, red = +85C; unless otherwise noted.
10
3
2
1 OUTPUT (V)
1
ERROR (dB)
0.1 450 900 1900 2600 3500 5000 6000
08437-004
0
-1 450 900 1900 2600 3500 5000 6000 -20 -15 -10 -5 0 5 10 15
08437-007 08437-009
-2
0.01 -25
-20
-15
-10
-5
0
5
10
15
-3 -25
INPUT (dBm)
INPUT (dBm)
Figure 4. Output vs. Input Level, 450 MHz, 900 MHz, 1900 MHz, 2600 MHz, 3500 MHz, 5000 MHz, 6000 MHz Frequencies, 3.0 V Supply
2.0 1.8 1.6 1.4
OUTPUT (V)
Figure 7. Linearity Error vs. Input Level, 450 MHz, 900 MHz, 1900 MHz, 2600 MHz, 3500 MHz, 5000 MHz, 6000 MHz Frequencies, 3.0 V Supply
10
450 900 1900 2600 3500 5000 6000
OUTPUT (V)
1
1.2 1.0 0.8 0.6 0.4 0.2 0
08437-005
0.1
2.5V 2.7V 3.0V 3.3V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
-20
-15
-10
-5
0
5
10
15
INPUT (V rms)
INPUT (dBm)
Figure 5. Output vs. Input Level (Linear Scale), 450 MHz, 900 MHz, 1900 MHz, 2600 MHz, 3500 MHz, 5000 MHz, 6000 MHz Frequencies, 3.0 V Supply
2.5 100
Figure 8. Output vs. Input Level, 900 MHz Frequency, 2.5 V, 2.7 V, 3.0 V, and 3.3 V Supplies
700 1.4
CONVERSION GAIN (V/V rms)
2.0
80
600
1.2 1.0 SHUNT CAPACITANCE
500
1.5
60
400
0.8
1.0
40
300 SHUNT RESISTANCE
0.6
200 100
0.4 0.2 0 3.0
0.5
20
0 0 1k 2k 3k 4k 5k FREQUENCY (MHz)
08437-006
0 6k
0 0.5
1.0
1.5
2.0
2.5
FREQUENCY (GHz)
Figure 6. Conversion Gain and Intercept vs. Frequency, 3.0 V Supply at -40C, +25C, and +85C
Figure 9. Input Impedance vs. Frequency, 3.0 V Supply, at -40C, +25C, and +85C
Rev. 0 | Page 8 of 24
SHUNT CAPACITACE (pF)
SHUNT RESISTANCE ()
INTERCEPT (mV)
08437-008
0.01 -25
ADL5504
3 3
2
2
1 ERROR (dB) ERROR (dB)
08437-010
1
0
0
-1
-1
-2
-2
-20
-15
-10
-5
0
5
10
15
-20
-15
-10
-5
0
5
10
15
INPUT (dBm)
INPUT (dBm)
Figure 10. Output Temperature Drift from +25C Linear Reference for 50 Devices at -40C, +25C, and +85C, 450 MHz Frequency
3
Figure 13. Output Delta from +25C Output Voltage for 50 Devices at -40C and +85C, 450 MHz Frequency
3
2
2
1 ERROR (dB) ERROR (dB)
1
0
0
-1
-1
-2
-2
08437-011
-20
-15
-10
-5
0
5
10
15
-20
-15
-10
-5
0
5
10
15
INPUT (dBm)
INPUT (dBm)
Figure 11. Output Temperature Drift from +25C Linear Reference for 50 Devices at -40C, +25C, and +85C, 900 MHz Frequency
3
Figure 14. Output Delta from +25C Output Voltage for 50 Devices at -40C and +85C, 900 MHz Frequency
3
2
2
1 ERROR (dB) ERROR (dB)
1
0
0
-1
-1
-2
-2
08437-012
-20
-15
-10
-5
0
5
10
15
-20
-15
-10
-5
0
5
10
15
INPUT (dBm)
INPUT (dBm)
Figure 12. Output Temperature Drift from +25C Linear Reference for 50 Devices at -40C, +25C, and +85C, 1900 MHz Frequency
Figure 15. Output Delta from +25C Output Voltage for 50 Devices at -40C and +85C, 1900 MHz Frequency
Rev. 0 | Page 9 of 24
08437-015
-3 -25
-3 -25
08437-014
-3 -25
-3 -25
08437-013
-3 -25
-3 -25
ADL5504
3 3
2
2
1 ERROR (dB) ERROR (dB)
08437-016
1
0
0
-1
-1
-2
-2
-20
-15
-10
-5
0
5
10
15
-20
-15
-10
-5
0
5
10
15
INPUT (dBm)
INPUT (dBm)
Figure 16. Output Temperature Drift from +25C Linear Reference for 50 Devices at -40C, +25C, and +85C, 2600 MHz Frequency
3
Figure 19. Output Delta from +25C Output Voltage for 50 Devices at -40C and +85C, 2600 MHz Frequency
3
2
2
1 ERROR (dB) ERROR (dB)
1
0
0
-1
-1
-2
-2
08437-017
-20
-15
-10
-5
0
5
10
15
-20
-15
-10
-5
0
5
10
15
INPUT (dBm)
INPUT (dBm)
Figure 17. Output Temperature Drift from +25C Linear Reference for 50 Devices at -40C, +25C, and +85C, 3500 MHz Frequency
3
Figure 20. Output Delta from +25C Output Voltage for 50 Devices at -40C and +85C, 3500 MHz Frequency
3
2
2
1 ERROR (dB) ERROR (dB)
1
0
0
-1
-1
-2
-2
08437-018
-20
-15
-10
-5
0
5
10
15
-20
-15
-10
-5
0
5
10
15
INPUT (dBm)
INPUT (dBm)
Figure 18. Output Temperature Drift from +25C Linear Reference for 50 Devices at -40C, +25C, and +85C, 6000 MHz Frequency
Figure 21. Output Delta from +25C Output Voltage for 50 Devices at -40C and +85C, 6000 MHz Frequency
Rev. 0 | Page 10 of 24
08437-021
-3 -25
-3 -25
08437-020
-3 -25
-3 -25
08437-019
-3 -25
-3 -25
ADL5504
3
CW 12.2kbps, DPCCH (-5.46dB, 15kSPS) + DPDCH (0dB, 60kSPS), 3.4dB CF 144kbps, DPCCH (-11.48dB, 15kSPS) + DPDCH (0dB, 480kSPS), 3.3dB CF 768kbps, DPCCH (-11.48dB, 15kSPS) + DPDCH1 + 2 (0dB, 960kSPS), 5.8dB CF
3
2
2
CW PICH, 4.7dB PICH + FCH (9.6kbps), 4.8dB CF PICH + FCH (9.6kbps) + DCCH, 6.3dB CF PICH + FCH (9.6kbps) + SCH (153.6kbps), 6.7dB PICH + FCH (9.6kbps) + DCCH +SCH (153.6kbps), 7.6dB CF
1
1
ERROR (dB)
ERROR (dB)
DPCCH (-6.02dB, 15kSPS) + DPDCH (-4.08dB, 60kSPS) + HS-DPCCH (0dB, 15kSPS), 4.91dB CFDPCCH (-6.02dB, 15kSPS) + DPDCH (-11.48dB, 60kSPS) + HS-DPCCH (0dB, 15kSPS), 5.34dB CF DPCCH (-6.02dB, 15kSPS) + HS-DPCCH (0dB, 15kSPS), 5.44dB CF
08437-022
0
0
-1
-1
-2
-2
-20
-15
-10
-5
0
5
10
15
-20
-15
-10
-5
0
5
10
15
INPUT (dBm)
INPUT (dBm)
Figure 22. Error from CW Linear Reference vs. Input with Various W-CDMA Reverse Link Waveforms at 900 MHz, CFLTR = 10 nF, COUT = Open
3 CW TEST TEST TEST TEST TEST TEST MODEL 1 WITH 16 DPCH, MODEL 1 WITH 32 DPCH, MODEL 1 WITH 64 DPCH, MODEL 1 WITH 64 DPCH, MODEL 1 WITH 64 DPCH, MODEL 1 WITH 64 DPCH, 1 CARRIER 1 CARRIER 1 CARRIER 2 CARRIERS 3 CARRIERS 4 CARRIERS
Figure 25. Error from CW Linear Reference vs. Input with Various CDMA2000 Reverse Link Waveforms at 1900 MHz, CFLTR = 12 nF, COUT = Open
3 CW 16QAM RB1 16QAM RB10 16QAM RB100 QPSK RB1 QPSK RB10 QPSK RB100
2
2
1
1
ERROR (dB)
0
ERROR (dB)
0
-1
-1
-2
-2
08437-023
-20
-15
-10
-5
0
5
10
15
-20
-15
-10
-5
0
5
10
15
INPUT (dBm)
INPUT (dBm)
Figure 23. Error from CW Linear Reference vs. Input with Various W-CDMA Forward Link Waveforms at 2200 MHz, CFLTR = 10 nF, COUT = Open
3 CW BPSK, 11dB CF QPSK, 11dB CF 16QAM, 12dB CF 64QAM, 11dB CF
Figure 26. Error from CW Linear Reference vs. Input with Various LTE Reverse Link Waveforms at 2600 MHz, CFLTR = 12 nF, COUT = Open
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 INPUT (V rms) 2.5V
2
1
0
-1
-2
08437-024
-20
-15
-10
-5
0
5
10
15
INPUT (dBm)
Figure 24. Error from CW Linear Reference vs. Input with Various 802.16 OFDM Waveforms at 3500 MHz, 10 MHz Signal BW, and 256 Subcarriers for All Modulated Signals, CFLTR = 10 nF, COUT = Open
Figure 27. Supply Current vs. Input Level, 2.5 V, 3.0 V, and 3.3 V Supplies, 900 MHz Frequency, at -40C, +25C, and +85C
Rev. 0 | Page 11 of 24
08437-027
-3 -25
SUPPLY CURRENT (mA)
ERROR (dB)
08437-026
-3 -25
-3 -25
08437-025
-3 -25
-3 -25
ADL5504
PULSED RFIN 400mV rms RF INPUT 400mV rms RF INPUT ENBL
VRMS (150mV/DIV)
VRMS (150mV/DIV)
250mV rms 160mV rms
250mV rms
160mV rms 70mV rms
70mV rms
08437-028
4s/DIV
2s/DIV
Figure 28. Output Response to Various RF Input Pulse Levels, 3.0 V Supply, 900 MHz Frequency, CFLTR = Open, COUT = Open, ROUT = Open
Figure 31. Output Response to Enable Gating at Various RF Input Levels, 3.0 V Supply, 900 MHz Frequency, CFLTR = Open, COUT = Open, ROUT = Open
PULSED RFIN 400mV rms RF INPUT 400mV rms RF INPUT
ENBL
VRMS (150mV/DIV)
250mV rms
VRMS (150mV/DIV)
250mV rms
160mV rms
160mV rms
70mV rms
70mV rms
08437-029
10s/DIV
4s/DIV
Figure 29. Output Response to Various RF Input Pulse Levels, 3.0 V Supply, 900 MHz Frequency, CFLTR = 10 nF, COUT = Open, ROUT = Open
Figure 32. Output Response to Enable Gating at Various RF Input Levels, 3.0 V Supply, 900 MHz Frequency, CFLTR = 10 nF, COUT = Open, ROUT = Open
PULSED RFIN
ENBL
400mV rms RF INPUT
VRMS (150mV/DIV)
VRMS (150mV/DIV)
400mV rms RF INPUT
250mV rms 160mV rms 70mV rms
250mV rms 160mV rms 70mV rms
08437-030
10s/DIV
10s/DIV
Figure 30. Output Response to Various RF Input Pulse Levels, 3.0 V Supply, 900 MHz Frequency, CFLTR =Open, COUT = 10 nF, ROUT = 1 k
Figure 33. Output Response to Enable Gating at Various RF Input Levels, 3.0 V Supply, 900 MHz Frequency, CFLTR =Open, COUT = 10 nF, ROUT = 1 k
Rev. 0 | Page 12 of 24
08437-033
08437-032
08437-031
ADL5504 CIRCUIT DESCRIPTION
The ADL5504 employs two-stage detection. The critical aspect of this technical approach is the concept of first stripping the carrier to reveal the envelope and then performing the required analog computation of rms. For improved accuracy with more complex RF waveforms (with modulation components extending down into the kilohertz region), more filtering is necessary to supplement the on-chip, low-pass filter. For this reason, the FLTR pin is provided; a capacitor attached between this pin and VPOS can extend the averaging time to very low frequencies (see the Selecting the Square-Domain Filter and Output Low-Pass Filter section). Any external capacitor acts on a 1 k resistor to yield a new corner frequency for the rms filter (see Figure 1). Adequate filtering ensures the accuracy of the rms measurement; however, some ripple or ac residual can still be present on the dc output. To reduce this ripple, an external shunt capacitor can be used at the output to form a low-pass filter with the on-chip, 100 resistance (see the Selecting the Square-Domain Filter and Output Low-Pass Filter section).
RMS CIRCUIT DESCRIPTION AND FILTERING
The rms processing is executed using a proprietary translinear technique. This method is a mathematically accurate rms computing approach and allows achieving unprecedented rms accuracies for complex modulation signals irrespective of the crest factor of the input signal. An integrating filter capacitor performs the square-domain averaging. The VRMS output can be expressed as
T2
VRMS = A x
VIN x dt
2
T1
T2 - T1
OUTPUT BUFFER
A buffer takes the internal rms signal and amplifies it accordingly before it is output on the VRMS pin. The output stage of the rms buffer is a common source PMOS with a resistive load to provide a rail-to-rail output. The buffer has a 100 on-chip series resistance on the output, allowing for easy lowpass filtering.
Note that A is a scaling parameter that is determined by the on-chip resistor ratio, and there are no other scaling parameters involved in this computation, which means that the rms output is inherently free from any sources of error due to temperature, supply, and process variations.
FILTERING
An important aspect of rms-dc conversion is the need for averaging (the function is root-mean-square). The on-chip averaging in the square domain has a corner frequency of approximately 40 kHz and is sufficient for common modulation signals, such as CDMA-, CDMA2000-, WCDMA-, and QPSK-/ QAM-based OFDM (for example, LTE, WLAN, and WiMAX).
Rev. 0 | Page 13 of 24
ADL5504 APPLICATIONS INFORMATION
BASIC CONNECTIONS
Figure 34 shows the basic connections for the ADL5504. The device is powered by a single supply between 2.5 V and 3.3 V, with a quiescent current of 1.8 mA. The VPOS pin is decoupled using 100 pF and 0.1 F capacitors. Placing a single 75 resistor at the RF input provides a broadband match of 50 . More precise resistive or reactive matches can be applied for narrow frequency band use (see the RF Input Interfacing section). The rms averaging can be augmented by placing additional capacitance at CFLTR. The ac residual can be reduced further by increasing the output capacitance, COUT. The combination of the internal 100 output resistance and COUT produces a lowpass filter to reduce output ripple of the VRMS output (see the Selecting the Square-Domain Filter and Output Low-Pass Filter section for more details).
+VS = 2.5V TO 3.3V 0.1F 100pF
CFLTR
1
Resistive Tap RF Input
Figure 36 shows a technique for coupling the input signal into the ADL5504 that can be applicable when the input signal is much larger than the input range of the ADL5504. A series resistor combines with the input impedance of the ADL5504 to attenuate the input signal. Because this series resistor forms a divider with the frequency-dependent input impedance, the apparent gain changes greatly with frequency. However, this method has the advantage of very little power being tapped off in RF power transmission applications. If the resistor is large compared with the impedance of the transmission line, the VSWR of the system is relatively unaffected.
RF TRANSMISSION LINE
ADL5504
Figure 36. Attenuating the Input Signal
FLTR ENBL
6
ADL5504
2
The resistive tap or series resistance, RSERIES, can be expressed as
VRMS ROUT COUT
08437-034
VPOS
VRMS
5
RSERIES = RIN (1 - 10ATTN/20)/(10ATTN/20) where: RIN is the input resistance of RFIN. ATTN is the desired attenuation factor in decibels.
08437-036
RSERIES
RFIN
(1)
RFIN
R10 75
3
RFIN
COMM
4
Figure 34. Basic Connections for ADL5504
RF INPUT INTERFACING
The input impedance of the ADL5504 decreases with increasing frequency in both its resistive and capacitive components (see Figure 9). The resistive component varies from 370 at 900 MHz to about 240 at 2600 MHz. A number of options exist for input matching. For operation at multiple frequencies, a 75 shunt to ground, as shown in Figure 35, provides the best overall match. For use at a single frequency, a resistive or a reactive match can be used. By plotting the input impedance on a Smith chart, the best value for a resistive match can be calculated. (Both input impedance and input capacitance can vary by up to 20% around their nominal values.) Where VSWR is critical, the match can be improved with a series inductor placed before the shunt component.
RF TRANSMISSION LINE DIRECTIONAL COUPLER 50
For example, if a power amplifier with a maximum output power of 28 dBm is matched to the ADL5504 input at 5 dBm, then a -23 dB attenuation factor is required. At 900 MHz, the input resistance, RIN, is 370 . RSERIES = (370 )(1 - 10-23/20)/(10-23/20) = 4870 Thus, for an attenuation of -23 dB, a series resistance of approximately 4.87 k is needed. (2)
ATTN 75
RFIN
ADL5504
Figure 35. Input Interfacing to Directional Coupler
08437-035
Rev. 0 | Page 14 of 24
ADL5504
Multiple RF Inputs
Figure 37 shows a technique for combining multiple RF input signals to the ADL5504. Some applications can share a single detector for multiple bands. Three 16.5 resistors in a T network combine the three 50 terminations (including the ADL5504 with the shunt 75 matching component). The broadband resistive combiner ensures that each port of the T network sees a 50 termination. Because there are only 6 dB of isolation from one port of the combiner to the other ports, only one band should be active at a time.
BAND 1 DIRECTIONAL COUPLER 50
Output Swing
At 900 MHz, the VRMS output voltage is nominally 1.87x the input rms voltage (a conversion gain of 1.87 V/V rms). The output voltage swings from near ground to 2.5 V on a 3.0 V supply. Figure 8 shows the output swings of the ADL5504 to a CW input for various supply voltages. Only at the lowest supply voltage (2.5 V) is there a reduction in the dynamic range as the input headroom decreases.
Output Offset
The ADL5504 has a 1 dB error detection range of about 30 dB, as shown in Figure 10 to Figure 12 and Figure 16 to Figure 18. The error is referred to the best-fit line defined in the linear region of the output response (see the Device Calibration and Error Calculation section for more details). Below an input power of -18 dBm, the response is no longer linear and begins to lose accuracy. In addition, depending on the supply voltage, saturation may limit the detection accuracy above 12 dBm. Calibration points should be chosen in the linear region, avoiding the nonlinear ranges at the high and low extremes. Figure 38 shows a distribution of the output response vs. the input for multiple devices. The ADL5504 loses accuracy at low input powers as the output response begins to fan out. As the input power is reduced, the spread of the output response increases along with the error.
10
16.5 BAND 2 DIRECTIONAL COUPLER 50 16.5 16.5 RFIN 75
ADL5504
Figure 37. Combining Multiple RF Input Signals
LINEARITY
Because the ADL5504 is a linear responding device, plots of output voltage vs. input voltage result in a straight line (see Figure 4 and Figure 5) and the dynamic range in decibels (dB) is not clearly visible. It is more useful to plot the error on a logarithmic scale, as shown in Figure 7. The deviation of the plot from the ideal straight line characteristic is caused by input stage clipping at the high end and by signal offsets at the low end. However, offsets at the low end can be either positive or negative; therefore, the linearity error vs. input level plots (see Figure 7) can also trend upwards at the low end. Figure 10 to Figure 12 and Figure 16 to Figure 18 show error distributions for a large population of devices at specific frequencies over temperature. It is also apparent in Figure 7 that the error at the lower portion of the dynamic range tends to shift up as frequency is increased. This is due to the calibration points chosen, -14 dBm and +8 dBm (see the Device Calibration and Error Calculation section). The absolute value cell has an input impedance that varies with frequency. The result is a decrease in the actual voltage across the squaring cell as the frequency increases, reducing the conversion gain. The dynamic range is near constant over frequency, but with a decrease in conversion gain as frequency is increased.
08437-037
1
OUTPUT (V)
0.1
0.01
0.001
-20
-15
-10
-5
0
5
10
15
INPUT (dBm)
Figure 38. Output vs. Input Level Distribution of 50 Devices, 900 MHz Frequency, 3.0 V Supply
Although some devices follow the ideal linear response at very low input powers, not all devices continue the ideal linear regression to a near 0 V y-intercept. Some devices exhibit output responses that rapidly decrease and some flatten out. With no RF signal applied, the ADL5504 has a typical output offset of 10 mV (with a maximum of 100 mV) on VRMS.
Rev. 0 | Page 15 of 24
08437-038
0.0001 -25
ADL5504
OUTPUT DRIVE CAPABILITY AND BUFFERING
The ADL5504 is capable of sourcing a VRMS output current of approximately 3 mA. The output current is sourced through the on-chip, 100 series resistor; therefore, any load resistor forms a voltage divider with this on-chip resistance. It is recommended that the ADL5504 VRMS output drive high resistance loads to preserve output swing. If an application requires driving a low resistance load (as well as in cases where increasing the nominal conversion gain is desired), a buffering circuit is necessary.
100 90 80
AC RESIDUAL (mV p-p)
70 60 50 40 30 20 10 1 10 100 1000
08437-039
COUT
SELECTING THE SQUARE-DOMAIN FILTER AND OUTPUT LOW-PASS FILTER
The internal filter capacitor of the ADL5504 provides averaging in the square domain but leaves some residual ac on the output. Signals with high peak-to-average ratios, such as W-CDMA or CDMA2000, can produce ac residual levels on the ADL5504 VRMS dc output. To reduce the effects of these low frequency components in the waveforms, some additional filtering is required. The square-domain filter capacitance of the ADL5504 can be augmented by connecting a capacitor between Pin 1 (FLTR) and Pin 2 (VPOS). In addition, the VRMS output of the ADL5504 can be filtered directly by placing a capacitor between VRMS (Pin 5) and ground. The combination of the on-chip, 100 output series resistance and the external shunt capacitor forms a lowpass filter to reduce the residual ac. Figure 39 and Figure 40 show the effects on the residual ripple vs. the output and square-domain filter capacitor values at two communication standards with high peak-to-average ratios. Note that there is a trade-off between ac residual and response time. Large filter capacitances increase the turn-on and pulse response times (see Figure 28 to Figure 33). Figure 41 shows the effect of the two filtering options, the output filter and the square-domain filter capacitor, on the pulse response time of the ADL5504. For more information on the effects of the filter capacitances on the response, see the Power Consumption, Enable, and Power-On/Power-Off Response Time section.
AC RESIDUAL (mV p-p)
CFLTR
0 CAPACITANCE (nF)
Figure 39. AC Residual vs. CFLTR and COUT, W-CDMA Reverse Link (5.8 dB CF) Waveform
400 350 COUT 300 250 200 150 100 50 0 1 10 100 1000 CAPACITANCE (nF) CFLTR
Figure 40. AC Residual vs. CFLTR and COUT, W-CDMA Forward Link (11.7 dB CF) Waveform
1000 900 800 250 225 200 175 150 125 100 75
CFLTR RESPONSE TIME (s)
700 600 500 400 300 200 100
CFLTR COUT 1 10 100
50 25
08437-041
0 CAPACITANCE (nF)
0 1000
Figure 41. CFLTR and COUT Response Time vs. Capacitance
Rev. 0 | Page 16 of 24
COUT RESPONSE TIME (s)
08437-040
ADL5504
POWER CONSUMPTION, ENABLE, AND POWERON/POWER-OFF RESPONSE TIME
The quiescent current consumption of the ADL5504 varies linearly with the size of the input signal from approximately 1.8 mA for no signal up to 9 mA at an input level of 0.7 V rms (10 dBm, referred to 50 ). There is little variation in supply current across power supply voltage or temperature, as shown in Figure 27. The ADL5504 can be disabled either by pulling the ENBL (Pin 6) to COMM (Pin 4) or by removing the power supply to the device. Disabling the device via the ENBL function reduces the leakage current to less than 1 A. When the device is disabled, the output impedance increases to approximately 5.5 k on VRMS. The turn-on time and pulse response is strongly influenced by the sizes of the square-domain filter and the output shunt capacitor. Figure 42 shows a plot of the output response to an RF pulse on the RFIN pin, with a 0.1 F output filter capacitor and a no square-domain filter capacitor. The falling edge is particularly dependent on the output shunt capacitance, as shown in Figure 42.
PULSED RFIN PULSED RFIN
VRMS (150mV/DIV)
400mV rms RF INPUT
250mV rms 160mV rms 70mV rms
1ms/DIV
Figure 43. Output Response to Various RF Input Pulse Levels, 3 V Supply, 900 MHz Frequency, Square-Domain Filter Open, COUT = 0.1 F with Parallel 1 k
The square-domain filter improves the rms accuracy for high crest factors (see the Selecting the Square-Domain Filter and Output Low-Pass Filter section), but it can hinder the response time. For optimum response time and low ac residual, both the square-domain filter and the output filter should be used. The square-domain filter at FLTR can be reduced to improve response time, and the remaining ac residual can be decreased by using the output filter, which has a smaller time constant.
VRMS (150mV/DIV)
DEVICE CALIBRATION AND ERROR CALCULATION
400mV rms RF INPUT 250mV rms 160mV rms 70mV rms
1ms/DIV
Figure 42. Output Response to Various RF Input Pulse Levels, 3 V Supply, 900 MHz Frequency, Square-Domain Filter Open, COUT = 0.1 F
08437-042
Because slope and intercept vary from device to device, boardlevel calibration must be performed to achieve high accuracy. In general, calibration is performed by applying two input power levels to the ADL5504 and measuring the corresponding output voltages. The calibration points are generally chosen to be within the linear operating range of the device. The best-fit line is characterized by calculating the conversion gain (or slope) and intercept using the following equations: Gain = (VVRMS2 - VVRMS1)/(VIN2 - VIN1) Intercept = VVRMS1 - (Gain x VIN1) where: VINx is the rms input voltage to RFIN. VVRMSx is the voltage output at VRMS. Once gain and intercept are calculated, an equation can be written that allows calculation of an (unknown) input power based on the measured output voltage. VIN = (VVRMS - Intercept)/Gain (5) For an ideal (known) input power, the law conformance error of the measured data can be calculated as ERROR (dB) = 20 x log [(VVRMS, MEASURED - Intercept)/ (Gain x VIN, IDEAL)] (6) (3) (4)
To improve the falling edge of the enable and pulse responses, a resistor can be placed in parallel with the output shunt capacitor. The added resistance helps to discharge the output filter capacitor. Although this method reduces the power-off time, the added load resistor also attenuates the output (see the Output Drive Capability and Buffering section).
Rev. 0 | Page 17 of 24
08437-043
ADL5504
Figure 44 shows a plot of the error at 25C, the temperature at which the ADL5504 is calibrated. Note that the error is not 0; this is because the ADL5504 does not perfectly follow the ideal linear equation, even within its operating region. The error at the calibration points is, however, equal to 0 by definition. Figure 44 also shows error plots for the output voltage at -40C and +85C. These error plots are calculated using the gain and intercept at 25C. This is consistent with calibration in a mass production environment where calibration at temperature is not practical.
3
This plot is a useful tool for estimating temperature drift at a particular power level with respect to the (nonideal) response at ambient temperature. The linearity and dynamic range tend to be improved artificially with this type of plot because the ADL5504 does not perfectly follow the ideal linear equation (especially outside of its linear operating range). Achieving this level of accuracy in an end application requires calibration at multiple points in the operating range of the device. In some applications, very high accuracy is required at just one power level or over a reduced input range. For example, in a wireless transmitter, the accuracy of the high power amplifier (HPA) is most critical at or close to full power. The ADL5504 offers a tight error distribution in the high input power range, as shown in Figure 45. The high accuracy range, beginning around 2 dBm at 1900 MHz, offers 12 dB of 0.15 dB detection error over temperature. Multiple point calibration at ambient temperature in the reduced range offers precise power measurement with near 0 dB error from -40C to +85C.
3
2
1
ERROR (dB)
+85C
+25C
0 -40C -1
-2
2
INPUT (dBm)
ERROR (dB)
-20
-15
-10
-5
0
5
10
15
08437-044
-3 -25
1 +85C 0 +25C -1 -40C
Figure 44. Error from Linear Reference vs. Input at -40C, +25C, and +85C vs. +25C Linear Reference, 1900 MHz Frequency, 3.0 V Supply
CALIBRATION FOR IMPROVED ACCURACY
Another way of presenting the error function of the ADL5504 is shown in Figure 45. In this case, the decibel (dB) error at hot and cold temperatures is calculated with respect to the transfer function at ambient temperature. This is a key difference in comparison to Figure 44, in which the error was calculated with respect to the ideal linear transfer function at ambient temperature. When this alternative technique is used, the error at ambient temperature becomes equal to 0 by definition (see Figure 45).
-2
-20
-15
-10
-5
0
5
10
15
INPUT (dBm)
Figure 45. Error from +25C Output Voltage at -40C, +25C, and +85C After Ambient Normalization, 1900 MHz Frequency, 3.0 V Supply
Note that the high accuracy range center varies over frequency (see Figure 13 to Figure 15 and Figure 19 to Figure 21).
Rev. 0 | Page 18 of 24
08437-045
-3 -25
ADL5504
DRIFT OVER A REDUCED TEMPERATURE RANGE
Figure 46 shows the error over temperature for a 1900 MHz input signal. The error due to drift over temperature consistently remains within 0.20 dB and only begins to exceed this limit when the ambient temperature rises above +55C and drops below -30C. For all frequencies using a reduced temperature range, higher measurement accuracy is achievable.
1.00 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 -25 -40C -30C -20C -10C 0C +5C +15C +25C +35C +45C +55C +65C +75C +85C
DEVICE HANDLING
The wafer level chip scale package consists of solder bumps connected to the active side of the die. The part is Pb-free and RoHS compliant with 95.5% tin, 4.0% silver, and 0.5% copper solder bump composition. The WLCSP can be mounted on printed circuit boards using standard surface-mount assembly techniques; however, caution should be taken to avoid damaging the die. See the AN-617 Application Note, MicroCSP Wafer Level Chip Scale Package, for additional information. WLCSP devices are bumped die; therefore, the exposed die may be sensitive to light, which can influence specified limits. Lighting in excess of 600 lux can degrade performance.
ERROR (dB)
-20
-15
-10
-5
0
5
10
15
INPUT (dBm)
Figure 46. Typical Drift at 1900 MHz for Various Temperatures
08437-046
Rev. 0 | Page 19 of 24
ADL5504
EVALUATION BOARD
Figure 47 shows the schematic of the ADL5504 evaluation board. The board is powered by a single supply in the 2.5 V to 3.3 V range. The power supply is decoupled by 100 pF and 0.1 F capacitors. The device must be enabled by switching SW1A to the position labeled on. The RF input has a broadband match of 50 using a single 75 resistor at R7A. More precise matching at spot frequencies is possible (see the RF Input Interfacing section). Table 4 details the various configuration options of the evaluation board. Figure 48 shows the layout of the evaluation board.
C7A (OPEN) (P1 - B8) R9A (OPEN)
1
Land Pattern and Soldering Information
Pad diameters of 0.28 mm are recommended with a solder paste mask opening of 0.38 mm. For the RF input trace, a trace width of 0.30 mm is used, which corresponds to a 50 characteristic impedance for the dielectric material being used (FR4). All traces going to the pads are tapered down to 0.15 mm. For the RFIN line, the length of the tapered section is 0.20 mm.
SW1A VPOSA
VPOSA R8A (OPEN) R4A 0
R1A (OPEN)
R10A (OPEN)
P2
ENA
(P1 - B6)
FLTR
ENBL 6
R3A 0
C3A 10nF VPOSA C9A (OPEN)
2
ADL5504
VPOS VRMS 5
VRMSA
C2A 0.1F
C1A 100pF
3
C4A (OPEN) RFIN COMM 4
R2A (OPEN)
R5A (OPEN)
(P1 - B4)
RFINA
R7A 75
(P1 - B12)
Figure 47. Evaluation Board Schematic
Figure 48. Layout of Evaluation Board, Component Side
Rev. 0 | Page 20 of 24
08437-048
08437-047
R6A (OPEN)
C8A (OPEN)
VPOSA
(P1 - A1,B1)
C6 (OPEN)
C5 (OPEN)
ADL5504
Table 4. Evaluation Board Configuration Options
Component VPOSA, GNDA C1A, C2A, C7A, C8A, C9A, C5, C6 Description Ground and supply vector pins. Power supply decoupling. Nominal supply decoupling of 0.01 F and 100 pF. Default Condition Not applicable C1A = 100 pF (Size 0402) C2A = 0.1 F (Size 0402) C7A = C8A = open (Size 0805) C9A = open (Size 0402) C5 = C6 = open (Size 0402) C3A = 10 nF (Size 0402) R7A = 75 (Size 0402) R3A = 0 (Size 0402) R2A = open (Size 0402) C4A= open (Size 0402) R4A = 0 (Size 0402) R10A = open (Size 0402) SW1A = on position P2 = not installed P1 = not installed R1A = R5A = open (Size 0402) R6A = R9A = open (Size 0402) R8A = open (Size 0805)
C3A R7A C4A, R2A, R3A
SW1A, R4A, R10A, P2
Filter capacitor. The internal rms averaging capacitor can be augmented by placing additional capacitance in C3A. RF input interface. The 75 resistor at R7A combines with the ADL5504 internal input impedance to give a broadband input impedance of around 50 . Output filtering. The combination of the internal 100 output resistance and C4A produce a low-pass filter to reduce output ripple of the VRMS output. The output can be scaled down using the resistor divider pads, R2A and R3A. Device enable. When the SW1A is set to the on position, the ENBL pin is connected to the supply and the ADL5504 is in enable mode. In the opposite switch position, the ENBL pin is grounded (through the 0 resistor) putting the device in power-down mode. Alternate interface. The end connector, P1, allows access to various ADL5504 signals. These signal paths are only used during factory test and characterization.
P1, R1A, R5A, R6A, R8A, R9A
Rev. 0 | Page 21 of 24
ADL5504 OUTLINE DIMENSIONS
0.830 0.790 0.750 0.430 0.400 0.370 0.660 0.600 0.540 SEATING PLANE 0.280 0.260 0.240
2 1 A
BALL A1 IDENTIFIER
1.230 1.190 1.150
0.80 REF
B
0.40 REF
C
TOP VIEW
(BALL SIDE DOWN)
Figure 49. 6-Ball Wafer Level Chip Scale Package [WLCSP] (CB-6-8) Dimensions shown in millimeters
ORDERING GUIDE
Model ADL5504ACBZ-P7 1 ADL5504ACBZ-P21 ADL5504-EVALZ1
1
Temperature Range -40C to +85C -40C to +85C
Package Description 6-Ball WLCSP, 7" Pocket Tape and Reel 6-Ball WLCSP, 7" Pocket Tape and Reel Evaluation Board
Package Option CB-6-8 CB-6-8
Branding 3P 3P
082609-A
0.230 0.200 0.170
COPLANARITY 0.05
0.40 REF BOTTOM VIEW
(BALL SIDE UP)
Ordering Quantity 3,000 250
Z = RoHS Compliant Part.
Rev. 0 | Page 22 of 24
ADL5504 NOTES
Rev. 0 | Page 23 of 24
ADL5504 NOTES
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08437-0-10/09(0)
Rev. 0 | Page 24 of 24

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